WFG ch.10 Control Register A
| DCK | clock cycle of the WFG timer |
| TMD | WFG’s operation mode |
| GTEN | the CH_GATE signal for each channel of WFG |
| PSEL | the PPG timer unit to be used at each channel of WFG |
| PGEN | specifies how to reflect the CH_PPG signal that is input to each channel of WFG on WFG output |
| DMOD | specifies which polarity will be used to output the non-overlap signal |