Regviz

Fujitsu /MB9BF61xT /INTREQ /DRQSEL1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DRQSEL1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Fujitsu/MB9BF61xT/INTREQ/DRQSEL1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DRQSEL10)DRQSEL10 0 (DRQSEL11)DRQSEL11 0 (DRQSEL12)DRQSEL12 0 (DRQSEL13)DRQSEL13 0 (DRQSEL14)DRQSEL14

Description

DMA Request Select Register 1

Fields

DRQSEL10

Interrupt signal of EP1 DRQ of USB ch.1 is output to transfer request to DMAC through extended selector
DRQSEL11

Interrupt signal of EP2 DRQ of USB ch.1 is output to transfer request to DMAC through extended selector
DRQSEL12

Interrupt signal of EP3 DRQ of USB ch.1 is output to transfer request to DMAC through extended selector
DRQSEL13

Interrupt signal of EP4 DRQ of USB ch.1 is output to transfer request to DMAC through extended selector
DRQSEL14

Interrupt signal of EP5 DRQ of USB ch.1 is output to transfer request to DMAC through extended selector

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data