Extended Pin Function Setting Register 09
| QAIN0S | QAIN0S Input Select bits$ |
| QBIN0S | QBIN0S Input Select bits |
| QZIN0S | QZIN0S Input Select bits |
| QAIN1S | QAIN1S Input Select bits |
| QBIN1S | QBIN1S Input Select bits |
| QZIN1S | QZIN1S Input Select bits |
| ADTRG0S | ADTRG0 Input Select bits |
| ADTRG1S | ADTRG1 Input Select bits |
| ADTRG2S | ADTRG2 Input Select bits |
| CRX0S | CRX0S Input Select bits |
| CTX0E | CTX0E Output Select bits |
| CRX1S | CRX1S Input Select bits |
| CTX1E | CTX1E Output Select bits |