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Infineon /IMM100A /PORT3 /PPS

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Interpret as PPS

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https://regviz.com/r/Infineon/XMC1400/PORT3/PPS#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)PPS0 0 (value1)PPS1 0 (value1)PPS2 0 (value1)PPS3 0 (value1)PPS4

PPS4=value1, PPS1=value1, PPS3=value1, PPS0=value1, PPS2=value1

Description

Port 3 Pin Power Save Register

Fields

PPS0

Port 3 Pin Power Save Bit 0

0 (value1): Pin Power Save of P3.x is disabled.

1 (value2): Pin Power Save of P3.x is enabled.
PPS1

Port 3 Pin Power Save Bit 1

0 (value1): Pin Power Save of P3.x is disabled.

1 (value2): Pin Power Save of P3.x is enabled.
PPS2

Port 3 Pin Power Save Bit 2

0 (value1): Pin Power Save of P3.x is disabled.

1 (value2): Pin Power Save of P3.x is enabled.
PPS3

Port 3 Pin Power Save Bit 3

0 (value1): Pin Power Save of P3.x is disabled.

1 (value2): Pin Power Save of P3.x is enabled.
PPS4

Port 3 Pin Power Save Bit 4

0 (value1): Pin Power Save of P3.x is disabled.

1 (value2): Pin Power Save of P3.x is enabled.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data