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Infineon /XMC1200 /PPB /CPUID

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Interpret as CPUID

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)Revision 0PartNo0Architecture 0 (value1)Variant0Implementer

Variant=value1, Revision=value1

Description

CPUID Base Register

Fields

Revision

Revision Number

0 (value1): Patch 0
PartNo

Part Number of the Processor

3104 (value1): Cortex-M0
Architecture

Architecture

12 (value1): ARMv6-M
Variant

Variant Number

0 (value1): Revision 0
Implementer

Implementer Code

65 (value1): ARM

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data