Infineon /XMC1300 /POSIF0 /PCONF

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PCONF

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)FSEL 0 (value1)QDCM 0 (HIDG)HIDG 0 (value1)MCUE 0 (value1)INSEL0 0 (value1)INSEL1 0 (value1)INSEL2 0 (value1)DSEL 0 (value1)SPES 0 (value1)MSETS0 (value1)MSES 0 (value1)MSYNS 0 (value1)EWIS 0 (value1)EWIE 0 (value1)EWIL 0 (value1)LPC

EWIE=value1, MSES=value1, INSEL2=value1, FSEL=value1, LPC=value1, MSYNS=value1, EWIS=value1, INSEL1=value1, EWIL=value1, DSEL=value1, SPES=value1, MSETS=value1, INSEL0=value1, MCUE=value1, QDCM=value1

Description

CORDIC Coprocessor configuration

Fields

FSEL

Function Selector

0 (value1): Hall Sensor Mode enabled

1 (value2): Quadrature Decoder Mode enabled

2 (value3): stand-alone Multi-Channel Mode enabled

3 (value4): Quadrature Decoder and stand-alone Multi-Channel Mode enabled

QDCM

Position Decoder Mode selection

0 (value1): Position encoder is in Quadrature Mode

1 (value2): Position encoder is in Direction Count Mode.

HIDG

Idle generation enable

MCUE

Multi-Channel Pattern SW update enable

0 (value1): Multi-Channel pattern update is controlled via HW

1 (value2): Multi-Channel pattern update is controlled via SW

INSEL0

PhaseA/Hal input 1 selector

0 (value1): POSIFx.IN0A

1 (value2): POSIFx.IN0B

2 (value3): POSIFx.IN0C

3 (value4): POSIFx.IN0D

INSEL1

PhaseB/Hall input 2 selector

0 (value1): POSIFx.IN1A

1 (value2): POSIFx.IN1B

2 (value3): POSIFx.IN1C

3 (value4): POSIFx.IN1D

INSEL2

Index/Hall input 3 selector

0 (value1): POSIFx.IN2A

1 (value2): POSIFx.IN2B

2 (value3): POSIFx.IN2C

3 (value4): POSIFx.IN2D

DSEL

Delay Pin selector

0 (value1): POSIFx.HSDA

1 (value2): POSIFx.HSDB

SPES

Edge selector for the sampling trigger

0 (value1): Rising edge

1 (value2): Falling edge

MSETS

Pattern update signal select

0 (value1): POSIFx.MSETA

1 (value2): POSIFx.MSETB

2 (value3): POSIFx.MSETC

3 (value4): POSIFx.MSETD

4 (value5): POSIFx.MSETE

5 (value6): POSIFx.MSETF

6 (value7): POSIFx.MSETG

7 (value8): POSIFx.MSETH

MSES

Multi-Channel pattern update trigger edge

0 (value1): The signal used to enable a pattern update is active on the rising edge

1 (value2): The signal used to enable a pattern update is active on the falling edge

MSYNS

PWM synchronization signal selector

0 (value1): POSIFx.MSYNCA

1 (value2): POSIFx.MSYNCB

2 (value3): POSIFx.MSYNCC

3 (value4): POSIFx.MSYNCD

EWIS

Wrong Hall Event selection

0 (value1): POSIFx.EWHEA

1 (value2): POSIFx.EWHEB

2 (value3): POSIFx.EWHEC

3 (value4): POSIFx.EWHED

EWIE

External Wrong Hall Event enable

0 (value1): External wrong hall event emulation signal, POSIFx.EWHE[D…A], is disabled

1 (value2): External wrong hall event emulation signal, POSIFx.EWHE[D…A], is enabled.

EWIL

External Wrong Hall Event active level

0 (value1): POSIFx.EWHE[D…A] signal is active HIGH

1 (value2): POSIFx.EWHE[D…A] signal is active LOW

LPC

Low Pass Filters Configuration

0 (value1): Low pass filter disabled

1 (value2): Low pass of 1 clock cycle

2 (value3): Low pass of 2 clock cycles

3 (value4): Low pass of 4 clock cycles

4 (value5): Low pass of 8 clock cycles

5 (value6): Low pass of 16 clock cycles

6 (value7): Low pass of 32 clock cycles

7 (value8): Low pass of 64 clock cycles

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