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Infineon /XMC1300 /PPB /NVIC_IPR0

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Interpret as NVIC_IPR0

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https://regviz.com/r/Infineon/XMC1200/PPB/NVIC_IPR0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PRI_00PRI_10PRI_20PRI_3

Description

Interrupt Priority Register 0

Fields

PRI_0

Priority, Byte Offset 0
PRI_1

Priority, Byte Offset 1
PRI_2

Priority, Byte Offset 2
PRI_3

Priority, Byte Offset 3

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data