IDIV=value1, PCLKSEL=value1, VDDC2HIGH=value1, VDDC2LOW=value1, CNTADJ=value1
Clock Control Register
| FDIV | Fractional Divider Selection |
| IDIV | Divider Selection 0 (value1): Divider is bypassed. 1 (value2): 1; MCLK = 32 MHz 2 (value3): 2; MCLK = 16 MHz 3 (value4): 3; MCLK = 10.67 MHz 4 (value5): 4; MCLK = 8 MHz 254 (value6): 254; MCLK = 126 kHz 255 (value7): 255; MCLK = 125.5 kHz |
| PCLKSEL | PCLK Clock Select 0 (value1): PCLK = MCLK 1 (value2): PCLK = 2 x MCLK |
| RTCCLKSEL | RTC Clock Select |
| CNTADJ | Counter Adjustment 0 (value1): 1 clock cycles of the DCO1, 64MHz clock 1 (value2): 2 clock cycles of the DCO1, 64MHz clock 2 (value3): 3 clock cycles of the DCO1, 64MHz clock 3 (value4): 4 clock cycles of the DCO1, 64MHz clock 4 (value5): 5 clock cycles of the DCO1, 64MHz clock 1022 (value6): 1023 clock cycles of the DCO1, 64MHz clock 1023 (value7): 1024 clock cycles of the DCO1, 64MHz clock |
| VDDC2LOW | VDDC too low 0 (value1): VDDC is not too low and the fractional divider input clock is running at the targeted frequency 1 (value2): VDDC is too low and the fractional divider input clock is not running at the targeted frequency |
| VDDC2HIGH | VDDC too high 0 (value1): VDDC is not too high 1 (value2): VDDC is too high |