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Infineon /XMC1300 /SCU_CLK /OSCCSR

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Interpret as OSCCSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)OSC2L 0 (value1)OSC2H 0 (value1)OWDRES 0 (value1)OWDEN

OSC2H=value1, OWDRES=value1, OWDEN=value1, OSC2L=value1

Description

Oscillator Control and Status Register

Fields

OSC2L

Oscillator Valid Low Status Bit

0 (value1): The OSC frequency is usable

1 (value2): The OSC frequency is not usable. Frequency is too low.
OSC2H

Oscillator Valid High Status Bit

0 (value1): The OSC frequency is usable

1 (value2): The OSC frequency is not usable. Frequency is too high.
OWDRES

Oscillator Watchdog Reset

0 (value1): The Oscillator Watchdog is not cleared and remains active

1 (value2): The Oscillator Watchdog is cleared and restarted. The OSC2L and OSC2H flag will be held in the last value until it is updated after 3 standby clock cycles.
OWDEN

Oscillator Watchdog Enable

0 (value1): The Oscillator Watchdog is disabled

1 (value2): The Oscillator Watchdog is enabled

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data