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Infineon /XMC1300 /SCU_CLK /PWRSVCR

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Interpret as PWRSVCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)FPD

FPD=value1

Description

Power Save Control Register

Fields

FPD

Flash Power Down

0 (value1): no effect

1 (value2): Flash power down when entering power save mode. Upon wake-up, CPU is able to fetch code from flash.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data