Infineon /XMC1300 /SCU_GENERAL /PASSWD

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Interpret as PASSWD

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)MODE 0 (value1)PROTS 0PASS

PROTS=value1, MODE=value1

Description

Password Register

Fields

MODE

Bit Protection Scheme Control Bits

0 (value1): Scheme disabled - direct access to the protected bits is allowed.

3 (value2): Scheme enabled - the bit field PASS has to be written with the passwords to open and close the access to the protected bits. (Default)

PROTS

Bit Protection Signal Status Bit

0 (value1): Software is able to write to all protected bits.

1 (value2): Software is unable to write to any of the protected bits.

PASS

Password Bits

19 (value2): Opens access to writing of all protected bits.

21 (value3): Closes access to writing of all protected bits.

24 (value1): Enables writing of the bit field MODE.

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