Regviz

Infineon /XMC1300 /SCU_GENERAL /PMTSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PMTSR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Infineon/XMC1400/SCU_GENERAL/PMTSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)MTENS

MTENS=value1

Description

Parity Memory Test Select Register

Fields

MTENS

Parity Test Enable Control for 16kbytes SRAM

0 (value1): standard operation

1 (value2): generate an inverted parity bit during a write operation

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data