Infineon /XMC1300 /SCU_RESET /RSTCON

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Interpret as RSTCON

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)ECCRSTEN 0 (value1)LOCRSTEN 0 (value1)SPERSTEN 0 (value1)U0PERSTEN 0 (value1)MRSTEN

ECCRSTEN=value1, MRSTEN=value1, SPERSTEN=value1, U0PERSTEN=value1, LOCRSTEN=value1

Description

RCU Reset Control Register

Fields

ECCRSTEN

Enable ECC Error Reset

0 (value1): No reset when ECC double bit error occur

1 (value2): Reset when ECC double bit error occur

LOCRSTEN

Enable Loss of Clock Reset

0 (value1): No reset when loss of clock occur

1 (value2): Reset when loss of clock occur

SPERSTEN

Enable 16kbytes SRAM Parity Error Reset

0 (value1): No reset when SRAM parity error occur

1 (value2): Reset when SRAM parity error occur

U0PERSTEN

Enable USIC0 SRAM Parity Error Reset

0 (value1): No reset when USIC0 memory parity error occur

1 (value2): Reset when USIC0 memory parity error occur

MRSTEN

Enable Master Reset

0 (value1): No effect

1 (value2): Triggered Master reset

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