Infineon /XMC1300 /SHS0 /TIMCFG0

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Interpret as TIMCFG0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)AT 0 (value1)FCRT0 (value1)SST0TGEN

SST=value1, AT=value1, FCRT=value1

Description

Timing Configuration Register 0

Fields

AT

Accelerated Timing

0 (value1): Compatible timing: Result available after standard conversion time

1 (value2): Accelerated timing: Result available as soon as converted

FCRT

Fast Compare Mode Response Time

0 (value1): Result after tADCI * 2

15 (value2): Result after tADCI * 32

SST

Short Sample Time

0 (value1): Compatible timing: Sample time is defined by DIVA and STC.

1 (value2): Sample time is tADC * 1

63 (value3): Sample time is tADC * 63

TGEN

Timing Generator

Links

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