PPPEN=value1, SCLKCFG=value1, TMEN=value1, SCLKOSEL=value1, CTQSEL=value1, MCLKCFG=value1, CLKSEL=value1
Baud Rate Generator Register
| CLKSEL | Clock Selection 0 (value1): The fractional divider frequency fFD is selected. 2 (value3): The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN. 3 (value4): Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S. |
| TMEN | Timing Measurement Enable 0 (value1): Timing measurement is disabled: The trigger signals DX0T and DX1T are ignored. 1 (value2): Timing measurement is enabled: The 10-bit counter is incremented by 1 with fPPP and stops counting when reaching its maximum value. If one of the trigger signals DX0T or DX1T become active, the counter value is captured into bit field CTV, the counter is cleared and a transmit shift event is generated. |
| PPPEN | Enable 2:1 Divider for fPPP 0 (value1): The 2:1 divider for fPPP is disabled. fPPP = fPIN 1 (value2): The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2. |
| CTQSEL | Input Selection for CTQ 0 (value1): fCTQIN = fPDIV 1 (value2): fCTQIN = fPPP 2 (value3): fCTQIN = fSCLK 3 (value4): fCTQIN = fMCLK |
| PCTQ | Pre-Divider for Time Quanta Counter |
| DCTQ | Denominator for Time Quanta Counter |
| PDIV | Divider Mode: Divider Factor to Generate fPDIV |
| SCLKOSEL | Shift Clock Output Select 0 (value1): SCLK from the baud rate generator is selected as the SCLKOUT input source. 1 (value2): The transmit shift clock from DX1 input stage is selected as the SCLKOUT input source. |
| MCLKCFG | Master Clock Configuration 0 (value1): The passive level is 0. 1 (value2): The passive level is 1. |
| SCLKCFG | Shift Clock Output Configuration 0 (value1): The passive level is 0 and the delay is disabled. 1 (value2): The passive level is 1 and the delay is disabled. 2 (value3): The passive level is 0 and the delay is enabled. 3 (value4): The passive level is 1 and the delay is enabled. |