DFEN=value1, SFSEL=value1, DSEL=value1, DPOL=value1, CM=value1, DCEN=value1, DSEN=value1, INSW=value1, DXS=value1
Input Control Register 1
DSEL | Data Selection for Input Signal 0 (value1): The data input DX1A is selected. 1 (value2): The data input DX1B is selected. 2 (value3): The data input DX1C is selected. 3 (value4): The data input DX1D is selected. 4 (value5): The data input DX1E is selected. 5 (value6): The data input DX1F is selected. 6 (value7): The data input DX1G is selected. 7 (value8): The data input is always 1. |
DCEN | Delay Compensation Enable 0 (value1): The receive shift clock is dependent on INSW selection. 1 (value2): The receive shift clock is connected to the selected data input line. This setting is used if delay compensation is required in SSC and IIS protocols, else DCEN should always be 0. |
INSW | Input Switch 0 (value1): The input of the data shift unit is controlled by the protocol pre-processor. 1 (value2): The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor. |
DFEN | Digital Filter Enable 0 (value1): The input signal is not digitally filtered. 1 (value2): The input signal is digitally filtered. |
DSEN | Data Synchronization Enable 0 (value1): The un-synchronized signal can be taken as input for the data shift unit. 1 (value2): The synchronized signal can be taken as input for the data shift unit. |
DPOL | Data Polarity for DXn 0 (value1): The input signal is not inverted. 1 (value2): The input signal is inverted. |
SFSEL | Sampling Frequency Selection 0 (value1): The sampling frequency is fPERIPH. 1 (value2): The sampling frequency is fFD. |
CM | Combination Mode 0 (value1): The trigger activation is disabled. 1 (value2): A rising edge activates DX1T. 2 (value3): A falling edge activates DX1T. 3 (value4): Both edges activate DX1T. |
DXS | Synchronized Data Value 0 (value1): The current value of DX1S is 0. 1 (value2): The current value of DX1S is 1. |