Infineon /XMC1300 /USIC0_CH0 /INPR

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Interpret as INPR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)TSINP0TBINP0RINP0AINP0 (value1)PINP

PINP=value1, TSINP=value1

Description

Interrupt Node Pointer Register

Fields

TSINP

Transmit Shift Interrupt Node Pointer

0 (value1): Output SR0 becomes activated.

1 (value2): Output SR1 becomes activated.

2 (value3): Output SR2 becomes activated.

3 (value4): Output SR3 becomes activated.

4 (value5): Output SR4 becomes activated.

5 (value6): Output SR5 becomes activated.

TBINP

Transmit Buffer Interrupt Node Pointer

RINP

Receive Interrupt Node Pointer

AINP

Alternative Receive Interrupt Node Pointer

PINP

Transmit Shift Interrupt Node Pointer

0 (value1): Output SR0 becomes activated.

1 (value2): Output SR1 becomes activated.

2 (value3): Output SR2 becomes activated.

3 (value4): Output SR3 becomes activated.

4 (value5): Output SR4 becomes activated.

5 (value6): Output SR5 becomes activated.

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