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Infineon /XMC1300 /USIC0_CH0 /OUTDR

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Interpret as OUTDR

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https://regviz.com/r/Infineon/XMC1400/USIC0_CH0/OUTDR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DSR0RCI

Description

Receiver Buffer Output Register L for Debugger

Fields

DSR

Data from Shift Register
RCI

Receive Control Information from Shift Register

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data