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Infineon /XMC1300 /USIC0_CH0 /OUTR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as OUTR

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https://regviz.com/r/Infineon/XMC1400/USIC0_CH0/OUTR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DSR0RCI

Description

Receiver Buffer Output Register

Fields

DSR

Received Data
RCI

Receiver Control Information

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data