TIWEN=value1, SELO=value1, DX2TIEN=value1, SLPHSEL=value1, MSLSIEN=value1, PARIEN=value1, MCLK=value1, CTQSEL1=value1, FEM=value1, SELINV=value1, SELCTR=value1, MSLSEN=value1
Protocol Control Register [SSC Mode]
| MSLSEN | MSLS Enable 0 (value1): The MSLS generation is disabled (MSLS = 0). This is the setting for SSC slave mode. 1 (value2): The MSLS generation is enabled. This is the setting for SSC master mode. |
| SELCTR | Select Control 0 (value1): The coded select mode is enabled. 1 (value2): The direct select mode is enabled. |
| SELINV | Select Inversion 0 (value1): The SELO outputs have the same polarity as the MSLS signal (active high). 1 (value2): The SELO outputs have the inverted polarity to the MSLS signal (active low). |
| FEM | Frame End Mode 0 (value1): The current data frame is considered as finished when the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data (TDV = 0). 1 (value2): The MSLS signal is kept active also while no new data is available and no other end of frame condition is reached. In this case, the software can accept delays in delivering the data without automatic deactivation of MSLS in multi-word data frames. |
| CTQSEL1 | Input Frequency Selection 0 (value1): fCTQIN = fPDIV 1 (value2): fCTQIN = fPPP 2 (value3): fCTQIN = fSCLK 3 (value4): fCTQIN = fMCLK |
| PCTQ1 | Divider Factor PCTQ1 for Tiw and Tnf |
| DCTQ1 | Divider Factor DCTQ1 for Tiw and Tnf |
| PARIEN | Parity Error Interrupt Enable 0 (value1): A protocol interrupt is not generated with the detection of a parity error. 1 (value2): A protocol interrupt is generated with the detection of a parity error. |
| MSLSIEN | MSLS Interrupt Enable 0 (value1): A protocol interrupt is not generated if a change of signal MSLS is detected. 1 (value2): A protocol interrupt is generated if a change of signal MSLS is detected. |
| DX2TIEN | DX2T Interrupt Enable 0 (value1): A protocol interrupt is not generated if DX2T is activated. 1 (value2): A protocol interrupt is generated if DX2T is activated. |
| SELO | Select Output 0 (value1): The corresponding SELOx line cannot be activated. 1 (value2): The corresponding SELOx line can be activated (according to the mode selected by SELCTR). |
| TIWEN | Enable Inter-Word Delay Tiw 0 (value1): No delay between data words of the same frame. 1 (value2): The inter-word delay Tiw is enabled and introduced between data words of the same frame. |
| SLPHSEL | Slave Mode Clock Phase Select 0 (value1): Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge. 1 (value2): The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are always latched in with the leading edge. |
| MCLK | Master Clock Enable 0 (value1): The MCLK generation is disabled and output MCLK = 0. 1 (value2): The MCLK generation is enabled. |