SRBTM=value1, LOF=value1, SRBIEN=value1, RNM=value1, RBERIEN=value1, SRBTEN=value1, ARBIEN=value1, SIZE=value1, RCIM=value1, ARBINP=value1, SRBINP=value1
Receiver Buffer Control Register
| DPTR | Data Pointer |
| LIMIT | Limit For Interrupt Generation |
| SRBTM | Standard Receive Buffer Trigger Mode 0 (value1): Trigger mode 0: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=RBCTR.LIMIT. 1 (value2): Trigger mode 1: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=0. |
| SRBTEN | Standard Receive Buffer Trigger Enable 0 (value1): The standard receive buffer event trigger through bit TRBSR.SRBT is disabled. 1 (value2): The standard receive buffer event trigger through bit TRBSR.SRBT is enabled. |
| SRBINP | Standard Receive Buffer Interrupt Node Pointer 0 (value1): Output SR0 becomes activated. 1 (value2): Output SR1 becomes activated. 2 (value3): Output SR2 becomes activated. 3 (value4): Output SR3 becomes activated. 4 (value5): Output SR4 becomes activated. 5 (value6): Output SR5 becomes activated. |
| ARBINP | Alternative Receive Buffer Interrupt Node Pointer 0 (value1): Output SR0 becomes activated. 1 (value2): Output SR1 becomes activated. 2 (value3): Output SR2 becomes activated. 3 (value4): Output SR3 becomes activated. 4 (value5): Output SR4 becomes activated. 5 (value6): Output SR5 becomes activated. |
| RCIM | Receiver Control Information Mode 0 (value1): RCI[4] = PERR, RCI[3:0] = WLEN 1 (value2): RCI[4] = SOF, RCI[3:0] = WLEN 2 (value3): RCI[4] = 0, RCI[3:0] = WLEN 3 (value4): RCI[4] = PERR, RCI[3] = PAR, RCI[2:1] = 00B, RCI[0] = SOF |
| SIZE | Buffer Size 0 (value1): The FIFO mechanism is disabled. The buffer does not accept any request for data. 1 (value2): The FIFO buffer contains 2 entries. 2 (value3): The FIFO buffer contains 4 entries. 3 (value4): The FIFO buffer contains 8 entries. 4 (value5): The FIFO buffer contains 16 entries. 5 (value6): The FIFO buffer contains 32 entries. 6 (value7): The FIFO buffer contains 64 entries. |
| RNM | Receiver Notification Mode 0 (value1): Filling level mode: A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTR (LOF = 0) or due to a new received data word (LOF = 1). 1 (value2): RCI mode: A standard receive buffer event occurs when register OUTR is updated with a new value if the corresponding value in OUTR.RCI[4] = 0. If OUTR.RCI[4] = 1, an alternative receive buffer event occurs instead of the standard receive buffer event. |
| LOF | Buffer Event on Limit Overflow 0 (value1): A standard receive buffer event occurs when the filling level equals the limit value and gets lower due to a read access from OUTR. 1 (value2): A standard receive buffer event occurs when the filling level equals the limit value and gets bigger due to the reception of a new data word. |
| ARBIEN | Alternative Receive Buffer Interrupt Enable 0 (value1): The alternative receive buffer interrupt generation is disabled. 1 (value2): The alternative receive buffer interrupt generation is enabled. |
| SRBIEN | Standard Receive Buffer Interrupt Enable 0 (value1): The standard receive buffer interrupt generation is disabled. 1 (value2): The standard receive buffer interrupt generation is enabled. |
| RBERIEN | Receive Buffer Error Interrupt Enable 0 (value1): The receive buffer error interrupt generation is disabled. 1 (value2): The receive buffer error interrupt generation is enabled. |