Infineon /XMC1300 /USIC0_CH0 /TBCTR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TBCTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DPTR0LIMIT0 (value1)STBTM 0 (value1)STBTEN 0 (value1)STBINP 0 (value1)ATBINP 0 (value1)SIZE0 (value1)LOF 0 (value1)STBIEN 0 (value1)TBERIEN

STBIEN=value1, LOF=value1, STBINP=value1, STBTEN=value1, TBERIEN=value1, SIZE=value1, STBTM=value1, ATBINP=value1

Description

Transmitter Buffer Control Register

Fields

DPTR

Data Pointer

LIMIT

Limit For Interrupt Generation

STBTM

Standard Transmit Buffer Trigger Mode

0 (value1): Trigger mode 0: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.LIMIT.

1 (value2): Trigger mode 1: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.SIZE.

STBTEN

Standard Transmit Buffer Trigger Enable

0 (value1): The standard transmit buffer event trigger through bit TRBSR.STBT is disabled.

1 (value2): The standard transmit buffer event trigger through bit TRBSR.STBT is enabled.

STBINP

Standard Transmit Buffer Interrupt Node Pointer

0 (value1): Output SR0 becomes activated.

1 (value2): Output SR1 becomes activated.

2 (value3): Output SR2 becomes activated.

3 (value4): Output SR3 becomes activated.

4 (value5): Output SR4 becomes activated.

5 (value6): Output SR5 becomes activated.

ATBINP

Alternative Transmit Buffer Interrupt Node Pointer

0 (value1): Output SR0 becomes activated.

1 (value2): Output SR1 becomes activated.

2 (value3): Output SR2 becomes activated.

3 (value4): Output SR3 becomes activated.

4 (value5): Output SR4 becomes activated.

5 (value6): Output SR5 becomes activated.

SIZE

Buffer Size

0 (value1): The FIFO mechanism is disabled. The buffer does not accept any request for data.

1 (value2): The FIFO buffer contains 2 entries.

2 (value3): The FIFO buffer contains 4 entries.

3 (value4): The FIFO buffer contains 8 entries.

4 (value5): The FIFO buffer contains 16 entries.

5 (value6): The FIFO buffer contains 32 entries.

6 (value7): The FIFO buffer contains 64 entries.

LOF

Buffer Event on Limit Overflow

0 (value1): A standard transmit buffer event occurs when the filling level equals the limit value and gets lower due to transmission of a data word.

1 (value2): A standard transmit buffer interrupt event occurs when the filling level equals the limit value and gets bigger due to a write access to a data input location INx.

STBIEN

Standard Transmit Buffer Interrupt Enable

0 (value1): The standard transmit buffer interrupt generation is disabled.

1 (value2): The standard transmit buffer interrupt generation is enabled.

TBERIEN

Transmit Buffer Error Interrupt Enable

0 (value1): The transmit buffer error interrupt generation is disabled.

1 (value2): The transmit buffer error interrupt generation is enabled.

Links

()