Infineon /XMC1300 /USIC0_CH0 /TRBSCR

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Interpret as TRBSCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)CSRBI 0 (value1)CRBERI 0 (value1)CARBI 0 (value1)CSTBI 0 (value1)CTBERI 0 (value1)CBDV 0 (value1)FLUSHRB 0 (value1)FLUSHTB

CTBERI=value1, CARBI=value1, FLUSHRB=value1, CSRBI=value1, FLUSHTB=value1, CBDV=value1, CRBERI=value1, CSTBI=value1

Description

Transmit/Receive Buffer Status Clear Register

Fields

CSRBI

Clear Standard Receive Buffer Event

0 (value1): No effect.

1 (value2): Clear TRBSR.SRBI.

CRBERI

Clear Receive Buffer Error Event

0 (value1): No effect.

1 (value2): Clear TRBSR.RBERI.

CARBI

Clear Alternative Receive Buffer Event

0 (value1): No effect.

1 (value2): Clear TRBSR.ARBI.

CSTBI

Clear Standard Transmit Buffer Event

0 (value1): No effect.

1 (value2): Clear TRBSR.STBI.

CTBERI

Clear Transmit Buffer Error Event

0 (value1): No effect.

1 (value2): Clear TRBSR.TBERI.

CBDV

Clear Bypass Data Valid

0 (value1): No effect.

1 (value2): Clear BYPCR.BDV.

FLUSHRB

Flush Receive Buffer

0 (value1): No effect.

1 (value2): The receive FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic.

FLUSHTB

Flush Transmit Buffer

0 (value1): No effect.

1 (value2): The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic.

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