TBUS=value1, RBERI=value1, STBT=value1, RFULL=value1, SRBI=value1, REMPTY=value1, RBUS=value1, TEMPTY=value1, TBERI=value1, STBI=value1, SRBT=value1, ARBI=value1, TFULL=value1
Transmit/Receive Buffer Status Register
| SRBI | Standard Receive Buffer Event 0 (value1): A standard receive buffer event has not been detected. 1 (value2): A standard receive buffer event has been detected. |
| RBERI | Receive Buffer Error Event 0 (value1): A receive buffer error event has not been detected. 1 (value2): A receive buffer error event has been detected. |
| ARBI | Alternative Receive Buffer Event 0 (value1): An alternative receive buffer event has not been detected. 1 (value2): An alternative receive buffer event has been detected. |
| REMPTY | Receive Buffer Empty 0 (value1): The receive buffer is not empty. 1 (value2): The receive buffer is empty. |
| RFULL | Receive Buffer Full 0 (value1): The receive buffer is not full. 1 (value2): The receive buffer is full. |
| RBUS | Receive Buffer Busy 0 (value1): The receive buffer information has been completely updated. 1 (value2): The OUTR update from the FIFO memory is ongoing. A read from OUTR will be delayed. FIFO pointers from the previous read are not yet updated. |
| SRBT | Standard Receive Buffer Event Trigger 0 (value1): A standard receive buffer event is not triggered using this bit. 1 (value2): A standard receive buffer event is triggered using this bit. |
| STBI | Standard Transmit Buffer Event 0 (value1): A standard transmit buffer event has not been detected. 1 (value2): A standard transmit buffer event has been detected. |
| TBERI | Transmit Buffer Error Event 0 (value1): A transmit buffer error event has not been detected. 1 (value2): A transmit buffer error event has been detected. |
| TEMPTY | Transmit Buffer Empty 0 (value1): The transmit buffer is not empty. 1 (value2): The transmit buffer is empty. |
| TFULL | Transmit Buffer Full 0 (value1): The transmit buffer is not full. 1 (value2): The transmit buffer is full. |
| TBUS | Transmit Buffer Busy 0 (value1): The transmit buffer information has been completely updated. 1 (value2): The FIFO memory update after write to INx is ongoing. A write to INx will be delayed. FIFO pointers from the previous INx write are not yet updated. |
| STBT | Standard Transmit Buffer Event Trigger 0 (value1): A standard transmit buffer event is not triggered using this bit. 1 (value2): A standard transmit buffer event is triggered using this bit. |
| RBFLVL | Receive Buffer Filling Level |
| TBFLVL | Transmit Buffer Filling Level |