Regviz

Infineon /XMC1300 /VADC_G0 /SYNCTR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SYNCTR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Infineon/XMC1400/VADC_G0/SYNCTR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)STSEL 0 (value1)EVALR1

STSEL=value1, EVALR1=value1

Description

Synchronization Control Register

Fields

STSEL

Start Selection

0 (value1): Kernel is synchronization master: Use own bitfield GxARBCFG.ANONC

1 (value2): Kernel is synchronization slave: Control information from input CI1
EVALR1

Evaluate Ready Input R1

0 (value1): No ready input control

1 (value2): Ready input R1 is considered for the start of a parallel conversion of this conversion group

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data