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Infineon /XMC4100 /CAN_NODE0 /NBTR

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Interpret as NBTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BRP0SJW0TSEG10TSEG20 (value1)DIV8

DIV8=value1

Description

Node Bit Timing Register

Fields

BRP

Baud Rate Prescaler
SJW

(Re) Synchronization Jump Width
TSEG1

Time Segment Before Sample Point
TSEG2

Time Segment After Sample Point
DIV8

Divide Prescaler Clock by 8

0 (value1): A time quantum lasts (BRP+1) clock cycles.

1 (value2): A time quantum lasts 8 (BRP+1) clock cycles.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data