Infineon /XMC4100 /FLASH0 /FCON

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Interpret as FCON

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)WSPFLASH 0 (value1)WSECPF 0 (value1)IDLE 0 (value1)ESLDIS 0 (value1)SLEEP 0 (value1)RPA 0 (value1)DCF 0 (value1)DDF 0 (value1)VOPERM 0 (value1)SQERM 0 (value1)PROERM 0 (value1)PFSBERM 0 (value1)PFDBERM 0 (value1)EOBM

WSPFLASH=value1, PROERM=value1, SLEEP=value1, IDLE=value1, PFDBERM=value1, EOBM=value1, DCF=value1, PFSBERM=value1, RPA=value1, ESLDIS=value1, VOPERM=value1, DDF=value1, WSECPF=value1, SQERM=value1

Description

Flash Configuration Register

Fields

WSPFLASH

Wait States for read access to PFLASH

0 (value1): PFLASH access in one clock cycle

1 (value2): PFLASH access in one clock cycle

2 (value3): PFLASH access in two clock cycles

3 (value4): PFLASH access in three clock cycles

15 (value5): PFLASH access in fifteen clock cycles.

WSECPF

Wait State for Error Correction of PFLASH

0 (value1): No additional wait state for error correction

1 (value2): One additional wait state for error correction during read access to Program Flash. If enabled, this wait state is only used for the first transfer of a burst transfer.

IDLE

Dynamic Flash Idle

0 (value1): Normal/standard Flash read operation

1 (value2): Dynamic idle of Program Flash enabled for power saving; static prefetching disabled

ESLDIS

External Sleep Request Disable

0 (value1): External sleep request signal input is enabled

1 (value2): Externally requested Flash sleep is disabled

SLEEP

Flash SLEEP

0 (value1): Normal state or wake-up

1 (value2): Flash sleep mode is requested

RPA

Read Protection Activated

0 (value1): The Flash-internal read protection is not activated. Bits DCF, DDF are not taken into account. Bits DCF, DDFx can be cleared

1 (value2): The Flash-internal read protection is activated. Bits DCF, DDF are enabled and evaluated.

DCF

Disable Code Fetch from Flash Memory

0 (value1): Code fetching from the Flash memory area is allowed.

1 (value2): Code fetching from the Flash memory area is not allowed. This bit is not taken into account while RPA=‘0’.

DDF

Disable Any Data Fetch from Flash

0 (value1): Data read access to the Flash memory area is allowed.

1 (value2): Data read access to the Flash memory area is not allowed. This bit is not taken into account while RPA=‘0’.

VOPERM

Verify and Operation Error Interrupt Mask

0 (value1): Interrupt not enabled

1 (value2): Flash interrupt because of Verify Error or Operation Error in Flash array (FSI) is enabled

SQERM

Command Sequence Error Interrupt Mask

0 (value1): Interrupt not enabled

1 (value2): Flash interrupt because of Sequence Error is enabled

PROERM

Protection Error Interrupt Mask

0 (value1): Interrupt not enabled

1 (value2): Flash interrupt because of Protection Error is enabled

PFSBERM

PFLASH Single-Bit Error Interrupt Mask

0 (value1): No Single-Bit Error interrupt enabled

1 (value2): Single-Bit Error interrupt enabled for PFLASH

PFDBERM

PFLASH Double-Bit Error Interrupt Mask

0 (value1): Double-Bit Error interrupt for PFLASH not enabled

1 (value2): Double-Bit Error interrupt for PFLASH enabled. Especially intended for margin check

EOBM

End of Busy Interrupt Mask

0 (value1): Interrupt not enabled

1 (value2): EOB interrupt is enabled

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