Infineon /XMC4100 /GPDMA0_CH0 /CTLL

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Interpret as CTLL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INT_EN)INT_EN 0DST_TR_WIDTH 0SRC_TR_WIDTH 0 (value1)DINC 0 (value1)SINC 0DEST_MSIZE 0SRC_MSIZE 0 (value1)SRC_GATHER_EN 0 (value1)DST_SCATTER_EN 0TT_FC0 (LLP_DST_EN)LLP_DST_EN 0 (LLP_SRC_EN)LLP_SRC_EN

DST_SCATTER_EN=value1, SRC_GATHER_EN=value1, DINC=value1, SINC=value1

Description

Control Register Low

Fields

INT_EN

Interrupt Enable Bit

DST_TR_WIDTH

Destination Transfer Width

SRC_TR_WIDTH

Source Transfer Width

DINC

Destination Address Increment

0 (value1): Increment

1 (value2): Decrement

2 (value3): No change

SINC

Source Address Increment

0 (value1): Increment

1 (value2): Decrement

2 (value3): No change

DEST_MSIZE

Destination Burst Transaction Length

SRC_MSIZE

Source Burst Transaction Length

SRC_GATHER_EN

Source gather enable

0 (value1): Gather disabled

1 (value2): Gather enabled

DST_SCATTER_EN

Destination scatter enable

0 (value1): Scatter disabled

1 (value2): Scatter enabled

TT_FC

Transfer Type and Flow Control

LLP_DST_EN

Linked List Pointer for Destination Enable

LLP_SRC_EN

Linked List Pointer for Source Enable

Links

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