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Infineon /XMC4100 /HRPWM0 /CSGCLRG

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Interpret as CSGCLRG

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https://regviz.com/r/Infineon/XMC4200/HRPWM0/CSGCLRG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CD0R)CD0R 0 (CC0R)CC0R 0 (CC0P)CC0P 0 (CD1R)CD1R 0 (CC1R)CC1R 0 (CC1P)CC1P 0 (CD2R)CD2R 0 (CC2R)CC2R 0 (CC2P)CC2P

Description

Global CSG run bit clear

Fields

CD0R

DAC0 run bit clear
CC0R

CMP0 run bit clear
CC0P

CMP0 passive level clear
CD1R

DAC1 run bit clear
CC1R

CMP1 run bit clear
CC1P

CMP1 passive level clear
CD2R

DAC2 run bit clear
CC2R

CMP2 run bit clear
CC2P

CMP2 passive level clear

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data