RegViz: Visualize MIRRSTS Bitfield

Infineon /XMC4100 /SCU_GENERAL /MIRRSTS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MIRRSTS

LPACCONF=value1, LPACTH1=value1, RTC_MSKSR=value1, RTC_ATIM0=value1, OSCULCTRL=value1, HINTCLR=value1, RTC_TIM1=value1, RTC_CLRSR=value1, OSCSICTRL=value1, HDCLR=value1, LPACCLR=value1, LPACSET=value1, RMX=value1, HDSET=value1, HINTSET=value1, LPACTH0=value1, RTC_TIM0=value1, RTC_CTR=value1, HDCR=value1, RTC_ATIM1=value1

Description

Mirror Write Status Register

Fields

HDCLR	HDCLR Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
HDSET	HDSET Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
HDCR	HDCR Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
OSCSICTRL	OSCSICTRL Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
OSCULCTRL	OSCULCTRL Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
RTC_CTR	RTC CTR Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
RTC_ATIM0	RTC ATIM0 Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
RTC_ATIM1	RTC ATIM1 Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
RTC_TIM0	RTC TIM0 Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
RTC_TIM1	RTC TIM1 Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
RMX	Retention Memory Access Register Update Status 0 (value1): Ready 1 (value2): Busy
RTC_MSKSR	RTC MSKSSR Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
RTC_CLRSR	RTC CLRSR Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
LPACCONF	LPACCONF Mirror Register Write Interrupt Set 0 (value1): Ready 1 (value2): Busy
LPACTH0	LPACTH0 Mirror Register Write Interrupt Set 0 (value1): Ready 1 (value2): Busy
LPACTH1	LPACTH1 Mirror Register Write Interrupt Set 0 (value1): Ready 1 (value2): Busy
LPACCLR	LPACCLR Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
LPACSET	LPACSET Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
HINTCLR	HINTCLR Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy
HINTSET	HINTSET Mirror Register Write Status 0 (value1): Ready 1 (value2): Busy

Links

()