RegViz: Visualize SRRAW Bitfield

Infineon /XMC4100 /SCU_INTERRUPT /SRRAW

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Interpret as SRRAW

RTC_TIM1=value1, OSCSICTRL=value1, LPACSET=value1, HDCLR=value1, PRWARN=value1, RTC_ATIM0=value1, RTC_TIM0=value1, RTC_CTR=value1, HINTSET=value1, OSCULCTRL=value1, LPACTH1=value1, RTC_ATIM1=value1, HINTCLR=value1, LPACTH0=value1, LPACCR=value1, HDCR=value1, LPACCLR=value1, RMX=value1, LPACST=value1, HINTST=value1, HDSET=value1

Description

SCU Raw Service Request Status

Fields

PRWARN	WDT pre-warning Interrupt Status Before Masking 0 (value1): Inactive 1 (value2): Active
PI	RTC Raw Periodic Interrupt Status Before Masking
AI	RTC Raw Alarm Interrupt Status Before Masking
DLROVR	DLR Request Overrun Interrupt Status Before Masking
LPACCR	LPACLR Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
LPACTH0	LPACTH0 Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
LPACTH1	LPACTH1 Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
LPACST	LPACST Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
LPACCLR	LPACCLR Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
LPACSET	LPACSET Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
HINTST	HINTST Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
HINTCLR	HINTCLR Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
HINTSET	HINTSET Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
HDCLR	HDCLR Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
HDSET	HDSET Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
HDCR	HDCR Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
OSCSICTRL	OSCSICTRL Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
OSCULCTRL	OSCULCTRL Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
RTC_CTR	RTC CTR Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
RTC_ATIM0	RTC ATIM0 Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
RTC_ATIM1	RTC ATIM1 Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
RTC_TIM0	RTC TIM0 Mirror Register Update Before Masking Status 0 (value1): Not updated 1 (value2): Update completed
RTC_TIM1	RTC TIM1 Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed
RMX	Retention Memory Mirror Register Update Status Before Masking 0 (value1): Not updated 1 (value2): Update completed

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