Infineon /XMC4200 /CCU40_CC40 /TC

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Interpret as TC

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)TCM 0 (value1)TSSM 0 (CLST)CLST 0 (value1)CMOD 0 (value1)ECM 0 (value1)CAPC 0 (value1)ENDM 0 (value1)STRM 0 (value1)SCE 0 (value1)CCS 0 (value1)DITHE 0 (value1)DIM 0 (value1)FPE 0 (value1)TRAPE 0 (value1)TRPSE 0 (value1)TRPSW 0 (value1)EMS 0 (value1)EMT 0 (value1)MCME

TRPSW=value1, CMOD=value1, TRAPE=value1, EMS=value1, FPE=value1, MCME=value1, ENDM=value1, DITHE=value1, EMT=value1, STRM=value1, SCE=value1, CAPC=value1, DIM=value1, TRPSE=value1, TSSM=value1, ECM=value1, TCM=value1, CCS=value1

Description

Slice Timer Control

Fields

TCM

Timer Counting Mode

0 (value1): Edge aligned mode

1 (value2): Center aligned mode

TSSM

Timer Single Shot Mode

0 (value1): Single shot mode is disabled

1 (value2): Single shot mode is enabled

CLST

Shadow Transfer on Clear

CMOD

Capture Compare Mode

0 (value1): Compare Mode

1 (value2): Capture Mode

ECM

Extended Capture Mode

0 (value1): Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only.

1 (value2): Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the ECRD.VPTR is cleared.

CAPC

Clear on Capture Control

0 (value1): Timer is never cleared on a capture event

1 (value2): Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event)

2 (value3): Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event)

3 (value4): Timer is always cleared in a capture event.

ENDM

Extended Stop Function Control

0 (value1): Clears the timer run bit only (default stop)

1 (value2): Clears the timer only (flush)

2 (value3): Clears the timer and run bit (flush/stop)

STRM

Extended Start Function Control

0 (value1): Sets run bit only (default start)

1 (value2): Clears the timer and sets run bit (flush/start)

SCE

Equal Capture Event enable

0 (value1): Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1

1 (value2): Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. and CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1

CCS

Continuous Capture Enable

0 (value1): The capture into a specific capture register is done with the rules linked with the full flags, described at .

1 (value2): The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back).

DITHE

Dither Enable

0 (value1): Dither is disabled

1 (value2): Dither is applied to the Period

2 (value3): Dither is applied to the Compare

3 (value4): Dither is applied to the Period and Compare

DIM

Dither input selector

0 (value1): Slice is using its own dither unit

1 (value2): Slice is connected to the dither unit of slice 0.

FPE

Floating Prescaler enable

0 (value1): Floating prescaler mode is disabled

1 (value2): Floating prescaler mode is enabled

TRAPE

TRAP enable

0 (value1): TRAP functionality has no effect on the output

1 (value2): TRAP functionality affects the output

TRPSE

TRAP Synchronization Enable

0 (value1): Exiting from TRAP state isn’t synchronized with the PWM signal

1 (value2): Exiting from TRAP state is synchronized with the PWM signal

TRPSW

TRAP State Clear Control

0 (value1): The slice exits the TRAP state automatically when the TRAP condition is not present

1 (value2): The TRAP state can only be exited by a SW request.

EMS

External Modulation Synchronization

0 (value1): External Modulation functionality is not synchronized with the PWM signal

1 (value2): External Modulation functionality is synchronized with the PWM signal

EMT

External Modulation Type

0 (value1): External Modulation functionality is clearing the CC4yST bit.

1 (value2): External Modulation functionality is gating the outputs.

MCME

Multi Channel Mode Enable

0 (value1): Multi Channel Mode is disabled

1 (value2): Multi Channel Mode is enabled

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