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Infineon /XMC4200 /FCE /CLC

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Interpret as CLC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISR)DISR 0 (DISS)DISS

Description

Clock Control Register

Fields

DISR

Module Disable Request Bit
DISS

Module Disable Status Bit

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data