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Infineon /XMC4200 /FLASH0 /MARP

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Interpret as MARP

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)MARGIN0 (value1)TRAPDIS

TRAPDIS=value1, MARGIN=value1

Description

Margin Control Register PFLASH

Fields

MARGIN

PFLASH Margin Selection

0 (value1): Standard (default) margin.

1 (value2): Tight margin for 0 (low) level. Suboptimal 0-bits are read as 1s.

4 (value3): Tight margin for 1 (high) level. Suboptimal 1-bits are read as 0s.
TRAPDIS

PFLASH Double-Bit Error Trap Disable

0 (value1): If a double-bit error occurs in PFLASH, a bus error trap is generated.

1 (value2): The double-bit error trap is disabled. Shall be used only during margin check

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data