Infineon /XMC4200 /GPDMA0 /CLEARDSTTRAN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLEARDSTTRAN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)CH0 0 (value1)CH1 0 (value1)CH2 0 (value1)CH3 0 (value1)CH4 0 (value1)CH5 0 (value1)CH6 0 (value1)CH7

CH5=value1, CH3=value1, CH1=value1, CH7=value1, CH2=value1, CH6=value1, CH4=value1, CH0=value1

Description

IntBlock Status

Fields

CH0

Clear Interrupt Status and Raw Status for channel 0

0 (value1): no effect

1 (value2): clear status

CH1

Clear Interrupt Status and Raw Status for channel 1

0 (value1): no effect

1 (value2): clear status

CH2

Clear Interrupt Status and Raw Status for channel 2

0 (value1): no effect

1 (value2): clear status

CH3

Clear Interrupt Status and Raw Status for channel 3

0 (value1): no effect

1 (value2): clear status

CH4

Clear Interrupt Status and Raw Status for channel 4

0 (value1): no effect

1 (value2): clear status

CH5

Clear Interrupt Status and Raw Status for channel 5

0 (value1): no effect

1 (value2): clear status

CH6

Clear Interrupt Status and Raw Status for channel 6

0 (value1): no effect

1 (value2): clear status

CH7

Clear Interrupt Status and Raw Status for channel 7

0 (value1): no effect

1 (value2): clear status

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