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Infineon /XMC4200 /GPDMA0 /RAWSRCTRAN

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Interpret as RAWSRCTRAN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0)CH0 0 (CH1)CH1 0 (CH2)CH2 0 (CH3)CH3 0 (CH4)CH4 0 (CH5)CH5 0 (CH6)CH6 0 (CH7)CH7

Description

Raw IntSrcTran Status

Fields

CH0

Raw Interrupt Status for channel 0
CH1

Raw Interrupt Status for channel 1
CH2

Raw Interrupt Status for channel 2
CH3

Raw Interrupt Status for channel 3
CH4

Raw Interrupt Status for channel 4
CH5

Raw Interrupt Status for channel 5
CH6

Raw Interrupt Status for channel 6
CH7

Raw Interrupt Status for channel 7

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data