Infineon /XMC4200 /GPDMA0 /SGLREQDSTREG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SGLREQDSTREG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0)CH0 0 (CH1)CH1 0 (CH2)CH2 0 (CH3)CH3 0 (CH4)CH4 0 (CH5)CH5 0 (CH6)CH6 0 (CH7)CH7 0 (value1)WE_CH0 0 (value1)WE_CH1 0 (value1)WE_CH2 0 (value1)WE_CH3 0 (value1)WE_CH4 0 (value1)WE_CH5 0 (value1)WE_CH6 0 (value1)WE_CH7

WE_CH1=value1, WE_CH6=value1, WE_CH0=value1, WE_CH5=value1, WE_CH2=value1, WE_CH4=value1, WE_CH7=value1, WE_CH3=value1

Description

Single Destination Transaction Request Register

Fields

CH0

Source request for channel 0

CH1

Source request for channel 1

CH2

Source request for channel 2

CH3

Source request for channel 3

CH4

Source request for channel 4

CH5

Source request for channel 5

CH6

Source request for channel 6

CH7

Source request for channel 7

WE_CH0

Source request write enable for channel 0

0 (value1): write disabled

1 (value2): write enabled

WE_CH1

Source request write enable for channel 1

0 (value1): write disabled

1 (value2): write enabled

WE_CH2

Source request write enable for channel 2

0 (value1): write disabled

1 (value2): write enabled

WE_CH3

Source request write enable for channel 3

0 (value1): write disabled

1 (value2): write enabled

WE_CH4

Source request write enable for channel 4

0 (value1): write disabled

1 (value2): write enabled

WE_CH5

Source request write enable for channel 5

0 (value1): write disabled

1 (value2): write enabled

WE_CH6

Source request write enable for channel 6

0 (value1): write disabled

1 (value2): write enabled

WE_CH7

Source request write enable for channel 7

0 (value1): write disabled

1 (value2): write enabled

Links

()