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Infineon /XMC4200 /PBA0 /STS

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Interpret as STS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)WERR

WERR=value1

Description

Peripheral Bridge Status Register

Fields

WERR

Bufferable Write Access Error

0 (value1): no write error occurred.

1 (value2): write error occurred, interrupt request is pending.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data