Infineon /XMC4200 /PPB /MPU_CTRL

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Interpret as MPU_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)ENABLE 0 (value1)HFNMIENA 0 (value1)PRIVDEFENA

HFNMIENA=value1, ENABLE=value1, PRIVDEFENA=value1

Description

MPU Control Register

Fields

ENABLE

Enable MPU

0 (value1): MPU disabled

1 (value2): MPU enabled.

HFNMIENA

Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers

0 (value1): MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit

1 (value2): the MPU is enabled during hard fault, NMI, and FAULTMASK handlers.

PRIVDEFENA

Enables privileged software access to the default memory map

0 (value1): If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault.

1 (value2): If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.

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