Infineon /XMC4200 /PPB /MPU_RASR

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Interpret as MPU_RASR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLE)ENABLE 0SIZE0 (value1)SRD0 (B)B0 (C)C0 (S)S0TEX0AP0 (value1)XN

SRD=value1, XN=value1

Description

MPU Region Attribute and Size Register

Fields

ENABLE

Region enable bit.

SIZE

MPU protection region size

SRD

Subregion disable bits

0 (value1): corresponding sub-region is enabled

1 (value2): corresponding sub-region is disabled

B

Memory access attribute

C

Memory access attribute

S

Shareable bit

TEX

Memory access attribute

AP

Access permission field

XN

Instruction access disable bit

0 (value1): instruction fetches enabled

1 (value2): instruction fetches disabled.

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