Infineon /XMC4200 /PPB /SCR

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Interpret as SCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)SLEEPONEXIT 0 (value1)SLEEPDEEP 0 (value1)SEVONPEND

SLEEPDEEP=value1, SLEEPONEXIT=value1, SEVONPEND=value1

Description

System Control Register

Fields

SLEEPONEXIT

Sleep on Exit

0 (value1): do not sleep when returning to Thread mode.

1 (value2): enter sleep, or deep sleep, on return from an ISR.

SLEEPDEEP

Sleep or Deep Sleep

0 (value1): sleep

1 (value2): deep sleep

SEVONPEND

Send Event on Pending bit:

0 (value1): only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded

1 (value2): enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

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