Infineon /XMC4200 /PPB /SYST_CSR

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Interpret as SYST_CSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)ENABLE 0 (value1)TICKINT 0 (value1)CLKSOURCE 0 (COUNTFLAG)COUNTFLAG

TICKINT=value1, ENABLE=value1, CLKSOURCE=value1

Description

SysTick Control and Status Register

Fields

ENABLE

Enable

0 (value1): counter disabled

1 (value2): counter enabled.

TICKINT

Tick Interrupt Enable

0 (value1): counting down to zero does not assert the SysTick exception request

1 (value2): counting down to zero to asserts the SysTick exception request.

CLKSOURCE

Indicates the clock source:

0 (value1): external clock

1 (value2): processor clock.

COUNTFLAG

Counter Flag

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