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Infineon /XMC4200 /SCU_CLK /CCUCLKCR

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Interpret as CCUCLKCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)CCUDIV

CCUDIV=value1

Description

CCU Clock Control Register

Fields

CCUDIV

CCU Clock Divider Enable

0 (value1): fCCU = fSYS

1 (value2): fCCU = fSYS / 2

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data