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Infineon /XMC4200 /SCU_CLK /PBCLKCR

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Interpret as PBCLKCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)PBDIV

PBDIV=value1

Description

Peripheral Bus Clock Control Register

Fields

PBDIV

PB Clock Divider Enable

0 (value1): fPERIPH = fCPU

1 (value2): fPERIPH = fCPU / 2

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data