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Infineon /XMC4200 /SCU_CLK /SYSCLKCR

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Interpret as SYSCLKCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SYSDIV0 (value1)SYSSEL

SYSSEL=value1

Description

System Clock Control Register

Fields

SYSDIV

System Clock Division Value
SYSSEL

System Clock Selection Value

0 (value1): fOFI clock

1 (value2): fPLL clock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data