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Infineon /XMC4200 /SCU_CLK /USBCLKCR

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Interpret as USBCLKCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0USBDIV 0 (value1)USBSEL

USBSEL=value1

Description

USB Clock Control Register

Fields

USBDIV

USB Clock Divider Value
USBSEL

USB Clock Selection Value

0 (value1): USB PLL Clock

1 (value2): PLL Clock

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data