LPACTH1=value1, HDSET=value1, RTC_TIM0=value1, LPACST=value1, OSCULCTRL=value1, OSCSICTRL=value1, RTC_CTR=value1, RTC_ATIM1=value1, LPACCLR=value1, LPACTH0=value1, LPACCR=value1, DLROVR=value1, RMX=value1, HINTST=value1, PI=value1, PRWARN=value1, AI=value1, HDCR=value1, HINTCLR=value1, RTC_ATIM0=value1, HINTSET=value1, RTC_TIM1=value1, HDCLR=value1, LPACSET=value1
SCU Service Request Clear
| PRWARN | WDT pre-warning Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| PI | RTC Periodic Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| AI | RTC Alarm Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| DLROVR | DLR Request Overrun Interrupt clear 0 (value1): No effect 1 (value2): Clear the status bit |
| LPACCR | LPACLR Mirror Register Update Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| LPACTH0 | LPACTH0 Mirror Register Update Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| LPACTH1 | LPACTH1 Mirror Register Update Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| LPACST | LPACST Mirror Register Update Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| LPACCLR | LPACCLR Mirror Register Update Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| LPACSET | LPACSET Mirror Register Update Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| HINTST | HINTST Mirror Register Update Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| HINTCLR | HINTCLR Mirror Register Update Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| HINTSET | HINTSET Mirror Register Update Interrupt Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| HDCLR | HDCLR Mirror Register Update Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| HDSET | HDSET Mirror Register Update Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| HDCR | HDCR Mirror Register Update Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| OSCSICTRL | OSCSICTRL Mirror Register Update Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| OSCULCTRL | OSCULCTRL Mirror Register Update Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| RTC_CTR | RTC CTR Mirror Register Update Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| RTC_ATIM0 | RTC ATIM0 Mirror Register Update Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| RTC_ATIM1 | RTC ATIM1 Mirror Register Update Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| RTC_TIM0 | RTC TIM0 Mirror Register Update Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| RTC_TIM1 | RTC TIM1 Mirror Register Update Clear 0 (value1): No effect 1 (value2): Clear the status bit |
| RMX | Retention Memory Mirror Register Update Clear 0 (value1): No effect 1 (value2): Clear the status bit |