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Infineon /XMC4200 /SCU_PLL /PLLCON1

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Interpret as PLLCON1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0K1DIV0NDIV0K2DIV0PDIV

Description

PLL Configuration 1 Register

Fields

K1DIV

K1-Divider Value
NDIV

N-Divider Value
K2DIV

K2-Divider Value
PDIV

P-Divider Value

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data