Infineon /XMC4200 /SCU_PLL /PLLCON2

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Interpret as PLLCON2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (value1)PINSEL 0 (value1)K1INSEL

K1INSEL=value1, PINSEL=value1

Description

PLL Configuration 2 Register

Fields

PINSEL

P-Divider Input Selection

0 (value1): PLL external oscillator selected

1 (value2): Backup clock fofi selected

K1INSEL

K1-Divider Input Selection

0 (value1): PLL external oscillator selected

1 (value2): Backup clock fofi selected

Links

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