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Infineon /XMC4200 /USIC0_CH0 /RBUF0

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Interpret as RBUF0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DSR0

Description

Receiver Buffer Register 0

Fields

DSR0

Data of Shift Registers 0[3:0]

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data